Beijing-based EVAS Intelligence has recently announced a significant Series C funding round, securing nearly RMB 2 billion (approximately $295 million), which elevates the company’s valuation to an estimated RMB 15 billion ($2.21 billion). This substantial capital injection is earmarked to expand the development and deployment of EVAS’s Epoch AI accelerator platform, a groundbreaking system built upon the open-source RISC-V instruction set architecture. The move underscores China’s intensifying commitment to fostering domestic semiconductor innovation and reducing reliance on foreign technologies, particularly in the face of escalating geopolitical tensions and export controls.
EVAS Intelligence Secures Substantial Funding for RISC-V AI Accelerator
The successful Series C funding round for EVAS Intelligence marks a pivotal moment for the burgeoning Chinese semiconductor industry. The $295 million investment is a robust vote of confidence from investors in EVAS’s vision and its technological approach, particularly its embrace of the RISC-V architecture. This capital will primarily fuel the expansion of the Epoch AI accelerator platform, which is designed to tackle complex AI workloads with high efficiency.
At the heart of the Epoch platform lies a specialized processor that marries the open RISC-V instruction set architecture with EVAS’s proprietary fifth-generation EVAMIND domain-specific architecture. Unlike traditional general-purpose GPUs, which rely on thousands of parallel processing cores, EVAMIND adopts an architecture more akin to dedicated AI accelerators. This design philosophy separates control functions from computational heavy lifting: embedded RISC-V cores are tasked with managing data movement, scheduling, and memory, while dedicated matrix and tensor engines execute the bulk of AI computations. This approach mirrors, in principle, Google’s Tensor Processing Units (TPUs), where general-purpose hardware orchestrates the system, leaving specialized hardware to perform the massive matrix operations critical for AI algorithms.
Further enhancing its capabilities, the Epoch platform supports block-quantized FP8, a technique vital for reducing memory capacity and bandwidth requirements during AI workload execution. EVAS has also revealed that its next-generation silicon, supporting even more aggressive EXFP4 and MXFP4 four-bit formats, has already completed its tape-out phase, signaling continuous innovation in processing efficiency.
Beyond individual accelerator chips, EVAS is also innovating at the system level. The company has developed a rack-scale RISC-V AI SuperNode designed to integrate numerous Epoch accelerators into a cohesive, powerful computing platform. This SuperNode leverages EVAS’s ELink interconnect, providing an impressive 3.2 Tbps of single-chip interconnect bandwidth, alongside an orthogonal backplane-free architecture and liquid cooling for optimal performance and density. Individual SuperNodes can accommodate between 64 and 128 Epoch chips in a symmetric scale-up configuration, with EVAS projecting that the wider architecture could eventually scale into massive clusters containing over 100,000 accelerator cards, demonstrating an ambitious roadmap for hyperscale AI infrastructure.
Recognizing that hardware prowess alone is insufficient, EVAS is simultaneously cultivating a comprehensive software ecosystem around Epoch. This includes EVACA, the KernelFab AI-assisted operator engine, and the VISA virtual instruction set architecture. This integrated software stack aims to streamline the development of AI operators and ensure software portability across different hardware generations, thereby simplifying the deployment of AI models for customers. However, critical details regarding Epoch’s manufacturing process and independent benchmark results (such as those from MLPerf) remain undisclosed, leaving its performance claims subject to future validation against established AI accelerators. The true test will be its ability to demonstrate sustained performance and reliability in large-scale production environments.
The Strategic Imperative: RISC-V in China’s Tech Sovereignty Quest
The significant investment in EVAS and its RISC-V-based architecture is a clear manifestation of China’s broader strategy to achieve technological self-reliance, particularly in the semiconductor sector. For nearly a decade, the relationship between the United States and China has been characterized by intense competition and strategic maneuvers across critical technologies, including semiconductors and artificial intelligence. The US has increasingly deployed export controls and restrictions on advanced semiconductor technology, prompting China to redouble its efforts to develop domestic alternatives and mitigate its dependence on foreign suppliers.
In this geopolitical context, RISC-V emerges as a particularly attractive and strategic choice for Chinese companies. Unlike proprietary instruction set architectures (ISAs) such as x86 (dominated by Intel and AMD) or ARM (ubiquitous in mobile but requiring licensing), RISC-V is an open standard. This means companies can implement and customize the ISA without incurring licensing fees or being subject to the commercial control of an architecture owner. This fundamental openness makes restricting access to RISC-V considerably more challenging, offering a pathway for China to circumvent geopolitical barriers.
Furthermore, RISC-V is not a purely Chinese initiative but is being developed by a vast international ecosystem of companies, universities, and engineers under the stewardship of RISC-V International. This global collaborative model allows China to build upon a universally supported architecture that benefits from worldwide contributions and software support, rather than having to develop an entirely new processor instruction set in isolation. This collaborative aspect accelerates development, broadens applicability, and strengthens the overall ecosystem, making it a powerful tool for nations seeking to enhance their technological autonomy without starting from scratch.
China has, unsurprisingly, increasingly embraced open architectures as a cornerstone of its technological future. EVAS exemplifies this strategy perfectly. By utilizing RISC-V cores for the control aspects of its accelerator, alongside its own EVAMIND architecture for computation, the company can develop a highly specialized AI processor that significantly reduces dependency on established Western processor architectures. While EVAS is not entirely insulated from the global semiconductor industry—manufacturing processes, EDA software, fabrication equipment, packaging technology, and memory components still involve international supply chains—the adoption of RISC-V removes one crucial dependency: the core processor instruction set architecture. As open architectures continue to mature and improve, attempts to restrict access to processor technology through architecture licensing become progressively less effective.
Navigating the Geopolitical Minefield: US-China Semiconductor Tensions
The rise of EVAS and its strategic embrace of RISC-V must be viewed within the broader framework of the US-China semiconductor rivalry, often described as a "cat and mouse" game. This competition intensified significantly during the Trump administration, with measures such as the blacklisting of Huawei Technologies in 2019, severely limiting its access to US technology and components. These initial actions were primarily aimed at curbing the technological advancement of specific Chinese companies deemed national security risks.
The Biden administration has largely continued and expanded these policies, notably with the imposition of sweeping export controls in October 2022. These regulations restrict China’s access to advanced semiconductor manufacturing equipment, certain high-end chips crucial for AI, and the expertise of US citizens working in the Chinese chip industry. The goal is explicitly to slow China’s progress in developing advanced computing capabilities for military and surveillance applications. Simultaneously, the US passed the CHIPS and Science Act in 2022, allocating over $50 billion in subsidies to boost domestic semiconductor manufacturing and research, aiming to strengthen its own supply chains and technological leadership.
In response, China has mobilized immense national resources. The "Made in China 2025" industrial policy, launched in 2015, explicitly targets self-sufficiency in key high-tech sectors, including integrated circuits. This has led to massive investments through the National Integrated Circuit Industry Investment Fund, commonly known as the "Big Fund," which has injected tens of billions of dollars into domestic chip manufacturers, equipment makers, and research institutions. The strategy is multi-pronged: developing indigenous manufacturing capabilities, nurturing domestic talent, fostering local design houses, and critically, exploring alternative technological pathways like open-source hardware.
The embrace of RISC-V is a direct consequence of these export controls. Each time access to a technology becomes restricted, Chinese companies are given a powerful incentive to innovate and find alternatives. This might involve developing entirely domestic manufacturing processes, creating replacement software ecosystems, or, as seen with EVAS, leveraging open architectures like RISC-V to build foundational technologies. This dynamic illustrates how restrictions, while intended to slow Chinese technological development, can inadvertently accelerate China’s drive towards greater self-reliance and the elimination of critical foreign dependencies.
Architectural Innovation: EVAS’s Epoch Platform and Domain-Specific AI
EVAS’s architectural choices for the Epoch platform represent a significant trend in the evolving landscape of AI hardware. For years, GPUs dominated AI acceleration due to their highly parallel processing capabilities, which were well-suited for the matrix multiplication inherent in neural networks. However, as AI models grow in complexity and demand for efficiency increases, the industry is shifting towards more specialized, domain-specific architectures (DSAs).
The EVAMIND architecture, combined with RISC-V, exemplifies this shift. By dedicating specific hardware (matrix and tensor engines) to the core AI computations and offloading control and management tasks to efficient RISC-V cores, EVAS aims to achieve superior performance per watt and per area compared to more generalized solutions. This fine-grained specialization allows for optimized data flow, reduced overhead, and better resource utilization for AI workloads. The ability to integrate custom instruction sets or extensions within RISC-V further enhances this specialization, allowing EVAS to tailor its processors precisely to the demands of deep learning algorithms.
The support for lower-precision floating-point formats like FP8, and the announced future support for EXFP4 and MXFP4, is also crucial. AI models, particularly during inference, can often tolerate reduced precision without significant loss of accuracy, while dramatically decreasing memory footprint, bandwidth requirements, and computational cost. This makes the chips more energy-efficient and scalable for large deployments.
The SuperNode concept, with its high-bandwidth ELink interconnect and liquid cooling, addresses the critical challenge of scaling AI workloads. As models grow, they require not just faster individual accelerators but also efficient communication between thousands of them. ELink’s 3.2 Tbps bandwidth per chip is vital for preventing bottlenecks in data transfer between accelerators, ensuring that the collective power of the SuperNode can be effectively harnessed. The ambition to scale to over 100,000 accelerator cards speaks to the enormous computational demands of future AI, including large language models and advanced generative AI, and EVAS’s intent to be a key player in this high-performance computing segment.
Challenges Ahead: Proving Performance and Scalability
Despite the impressive funding and ambitious technical roadmap, EVAS faces significant hurdles in establishing itself as a credible competitor in the global AI accelerator market. The most pressing challenge is the lack of independent validation for its performance claims. Without publicly disclosed manufacturing process details or third-party benchmark results from recognized platforms like MLPerf, it is impossible to directly compare Epoch’s capabilities with established accelerators from industry giants like NVIDIA, AMD, or Google.
Manufacturing capabilities represent another critical unknown. The production of advanced semiconductors requires access to state-of-the-art fabrication facilities (fabs), which are primarily concentrated in Taiwan (TSMC), South Korea (Samsung), and to a lesser extent, the US (Intel Foundry Services). Given the US export controls, EVAS’s ability to access leading-edge process nodes from non-Chinese fabs is highly constrained. If EVAS is relying on domestic Chinese fabs, these typically lag behind global leaders in terms of process technology, which could impact Epoch’s ultimate performance and power efficiency.
Furthermore, the maturity of EVAS’s software ecosystem, including EVACA, KernelFab, and VISA, is paramount. Developing a robust, developer-friendly software stack that can efficiently abstract hardware complexities and support a wide array of AI frameworks (like TensorFlow, PyTorch) is as critical as the hardware itself. Without strong software support, even the most powerful hardware can struggle to gain adoption. Customers need confidence that they can seamlessly deploy and optimize their AI models on EVAS accelerators.
Finally, the scalability claims, particularly the ability to combine thousands of accelerators into stable and high-performing clusters, need to be rigorously demonstrated. Interconnecting such a vast number of chips reliably, managing heat dissipation, and ensuring coherent data flow are immense engineering challenges. The $295 million investment reflects significant confidence, but the true test will come when EVAS can showcase production hardware successfully running large, real-world AI workloads at scale, providing tangible proof of its capabilities.
Broader Implications for Global Semiconductor Dynamics
The emergence of companies like EVAS, backed by substantial domestic funding and leveraging open standards like RISC-V, carries profound implications for the global semiconductor industry. Firstly, it accelerates the diversification of the global supply chain. As China reduces its dependence on foreign ISAs, it creates a parallel ecosystem that could, over time, become a significant force, potentially altering market dynamics and fostering new competition.
Secondly, it validates the power of open-source hardware. The success of RISC-V in a strategically critical sector like AI, particularly in a high-stakes geopolitical context, could inspire further adoption of open standards in other areas of hardware development. This could lead to a more fragmented but potentially more resilient global tech landscape, where innovation is less bottlenecked by proprietary licensing agreements.
Thirdly, it presents a long-term challenge to established proprietary ISA owners. If RISC-V continues its rapid ascent and proves its viability in high-performance computing, it could erode the market dominance of x86 and ARM in certain segments, forcing these incumbents to adapt their strategies, potentially by offering more flexible licensing models or by further innovating to maintain their competitive edge.
In the ongoing game of technological cat and mouse between the US and China, every dependency China eliminates strengthens its position and reduces the effectiveness of external pressure points. EVAS’s success in developing a competitive RISC-V-based AI accelerator would not only be a triumph for Chinese technological self-reliance but also a powerful testament to the potential of open standards to reshape the future of global semiconductor development. While challenges remain, the substantial investment and the strategic imperative behind EVAS position it as a critical player to watch in the evolving landscape of artificial intelligence and semiconductor innovation.
